1. Field of the Invention
The present invention relates to a frequency-locking device and, more particularly, to a frequency-locking device applied to universal serial bus (USB).
2. Description of the Related Art
As shown in FIG. 1A, the frequency-locking device 10 applied to universal serial bus data communication was disclosed in U.S. Pat. No. 6,297,705 and U.S. Pat. No. 6,407,641. With regard to the frequency-locking device 10, the output clock of an oscillator 142 is locked to the rate of an incoming data stream input. The object of this technology is to precisely lock the output clock of the oscillator 142 to the rate of the incoming data stream without utilizing any external elements and provide multiple tuning phases during a single data packet input via coarse and/or fine tuning.
Referring to FIG. 1A, the frequency-locking device 10 includes a control circuit 102 and an oscillator logic circuit 104. The control circuit 102 receives an incoming data stream DATA and an input signal PACKET and outputs a control signal CNTR and a correction signal FACTOR. The incoming data stream DATA includes a series of data packets. The frequency-locking device 10 measures the incoming data stream DATA in advance to generate the correction signal FACTOR, and then the correction signal FACTOR is used to alter the frequency of oscillation of the output signal OUT so that the frequency is locked to the rate of the incoming data stream DATA.
The control circuit 102 includes a control logic unit 103 and a counter circuit 106. The control logic unit 103 outputs an adjustment signal C/F and a control signal CNTR S/S to the counter circuit 106. Herein, the coarse or fine tuning of the frequency of oscillation of the output signal OUT is performed by the adjustment signal C/F with reference to the entire packet signal, i.e. the input signal PACKET. The control signal CNTR S/S is used to start or stop the counter circuit 106. The counter circuit 106 includes a calibration circuit such as the start/stop counter 150 and a look-up table 152. The look-up table 152 stores a fixed table of known characters in relation to adjustment of the frequency of oscillation of the output signal OUT and generates the correction signal FACTOR according to the adjustment signal C/F and the counts of the start/stop counter 150. As shown in FIG. 1B, the input signal PACKET is a token packet including digit information of sync field SYNC, packet identifier field PID, inverse packet identifier field, address field ADDR, Endpoint field ENDP, cyclic redundancy check field CRC, and data packet end field EOP.
The oscillator logic circuit 104 includes an oscillator control circuit 140 and an oscillator 142. The oscillator logic circuit 104 receives the control signal CNTR and the correction signal FACTOR and generates the output signal OUT. The control signal CNTR is used in determination of whether the frequency of oscillation of the output signal OUT is to be adjusted. The correction signal FACTOR represents an offset value (a multi-bit digital word) of a coarse tuning or fine tuning for the oscillating signal DIGOUT. The oscillator 142 generates the output signal OUT according to the oscillating signal DIGOUT.
The conventional coarse and fine tuning approach for the frequency-locking device 10 is described as follows. First, the start/stop counter 150 performs a coarse tuning by counting a pre-determined number of data edges of the input signal PACKET, feeding the counting value to the look-up table 152 for finding out correction factors corresponding to the counting values, and generating correction signal FACTOR for an adder 163. The adder 163 adds the value of the correction signal FACTOR to the originally set value ST and then sends the sum value to the oscillator setting unit 160 to generate oscillating signal DIGOUT. Then, fine tuning is recurrently applied to the output signal OUT for a longer period of time to perform more precise adjustment. In other words, the start/stop counter 150 starts fine tuning when the coarse tuning is completed and generates offset value by referring to the fine-tuning factors from the look-up table and adds or substrates the value of the signal DIGOUT with the offset value via the correction signal FACTOR. Thereby, the obtained oscillating frequency for the output signal OUT of the oscillator 142 fits the requirement, and the frequency of the output signal OUT is precisely locked to the rate of the incoming data stream.
However, the way of generating the correction signal FACTOR according to the all fields shown in FIG. 1B of the input signal PACKET of the universal serial bus makes the actual design and operation of circuit more complicated and defective. Since one-time reference to all of the digits of the token packet is required, the circuit design of the frequency-locking device 10 becomes more complicated. Besides, the great amount of memory space occupied by the look-up table inside the frequency-locking device 10 increases the memory cost for the frequency-locking device 10.